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| Layer | Details | |-------|---------| | | SIS‑SDK (C/C++) – based on Zephyr v3.7 with RISC‑V ports. Pre‑configured Makefile, CMake, and VS‑Code extensions. | | RTOS | Zephyr (default) – also supports FreeRTOS , Mbed‑OS , or bare‑metal . | | Toolchain | GNU RISC‑V Embedded (v13.2) – pre‑installed via sis-toolchain script (Linux/macOS/Windows). | | IDE Integration | VS‑Code (SIS‑Extension), Eclipse, PlatformIO, and Arduino‑RISC‑V Core (via community). | | Bootloader | Open‑Boot (secure, signed updates) – OTA via Wi‑Fi or QSPI flash swap. | | High‑level Libraries | sensors (BME280, LSM6DS3, etc.), network (LwIP, TinyTLS, MQTT‑SN), ML (TensorFlow‑Lite‑Micro 2.9). | | Python | MicroPython‑RISC‑V port (v1.22) – REPL over USB‑CDC. | | Examples | 60+ reference projects: blink, Wi‑Fi scanner, BLE beacon, LoRaWAN bridge, TensorFlow‑Lite inference, Edge‑AI camera pipeline (via OV2640 shield). | | Documentation | Full SIS001‑Hardware Reference Manual (PDF, 250 pages), API docs (Doxygen, HTML), Getting‑Started guide (PDF + video). | | Community | GitHub Org: github.com/sis001-dev – 5 k stars, 1 k forks, active issues. Discord server (12 k members) and monthly Hack‑athon webinars. | | Licensing | Hardware – Apache‑2.0; Firmware – Apache‑2.0 (or MIT for user projects). |